how to define a multi line macro in verilog? -

i relatively new verilog (a vhdl user), , in order improve skills built test environment using verilog (my qc use own env).

in env, emulate master force random stimuli on lines (i2c master).

since didn't want use real master , wanted 'well behaved' master, created following macros provide me i2c communications:

`define writechipid(addr)\ sda = 1\ #7500 sda = addr[3];\ #2500 sda = addr[2];\ #2500 sda = addr[1];\ #2500 sda = addr[0];\ #2500;  `define writedata(data)\ sda = data[7]\ #2500 sda = data[6];\ #2500 sda = data[5];\ #2500 sda = data[4];\ #2500 sda = data[3];\ #2500 sda = data[2];\ #2500 sda = data[1];\ #2500 sda = data[0];\ #2500 sda = 1;\ #2500; // time slave answer  `define readdata\ #sda = 1\ #20000 sda = 0;\ #2500; // master answer ack 

my problem that, when try use these macros compilation errors (using modelsim) saying have syntax error , have unexpected '[' should ';' using chipid macro , having unexpected '#' should ';' when using read\ write macros.

the usages try (and fail) are

`writechipid(`chipid)   

and

`writedata(rnddata)    

and

 `readdata 

last, not least: if write same lines without macro in code, compiles (only tried in 1 place, don't want 12 other places i'll need these macros...)

anyone have clue problem? i've been trying play macros no luck , verified have no white spaces stuck in middle.
looked multi-line macro examples , found similar things did didn't give answer.

thanks in advance repliers

edit
forgot saying: when take macro , remove input , use const values instead of input, works fine.

the syntax `define requires space after macro identifier/arguments.

`define writechipid(addr) \ sda = 1;\ #7500 sda = addr[3];\ #2500 sda = addr[2];\ #2500 sda = addr[1];\ #2500 sda = addr[0];\ #2500; 

as greg pointed out, calls using task.

task writechipid(input [3:0] addr); sda = 1; #7500 sda = addr[3]; #2500 sda = addr[2]; #2500 sda = addr[1]; #2500 sda = addr[0]; #2500; endtask