architecture - Latency between instructions -

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what latency between add , store instruction in mips pipeline . suppose have following 2 instructions.

add.d f4,f0,f2 s.d   f4,0(r1)

it given in book these 2 have latency of 2 cc , think need not any, if can bypass values in pipeline . value of f4 ready in 3rd cc , can forward value in f4 s.d instruction because r1 has nothing add.d instruction .

if wrong in thinking , correct latency ?


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