Using FOR loop in VHDL with a variable -

is there possible way create loop in form:

for in 0 some_var loop     // blah,blah end loop; 

if not, there alternative way create same loop? since while loops allows use variable limit, not synthesizeable in project.

thanks in advance,

bojan matovski

the variable works fine testbench applications.

for synthesis can same effect using static range , exit condition. set range maximum need.

for in 0 max_value loop   exit when = some_var ;   // blah,blah end loop; 

if synthesis tool chokes on this, file bug report. both 1076.6-1999 , 1076.6-2004 (vhdl rtl synthesis standards) indicate exit conditions supported "for" loops static range. may find support issues respect using loop label (1076.6-1999) indicates not supported.

if find bug (or lack of support) , not report it, vendor think feature don't care about, , hence, not invest in changing tool.