vhdl - generate targets in makefile depending on input text file -

i'm new here , @ using makefiles. have question please:

i had3 tests execute:

i added manually test1, test2 , test3 targets in make file this:

test1: compile_design  compile test1_testname.vhd >> log_file.log  simulate test1_testname

i did samething test2 , 3.

also added

all : test1 test2 test3

this works wonderfully.

now, want make makefile more portable: input file contains following information:

test1_testname test2_testname test3_testname

i want 3 targets added automatically , in general n targets if input file contains n lines.

you don't need use source file. may easier list targets @ top of makefile. then, using pattern rules, can have want following.

tests=test1_testname test2_testname test3_testname  all: $(tests)  %_testname: compile_design     compile $@.vhd >> log_file.log     simulate $@

you can note pattern rule defines targets test1_testname instead of shorter test1. avoid having % pattern rule.

if want use file list targets, can change first line with

tests=$(shell cat yoursourcefile)

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